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ACT-E128K32 High Speed 4 Megabit EEPROM Multichip Module
Features
Package Organized as 128K x 32
User
CIRCUIT TECHNOLOGY
www.aeroflex.com
4 Low Power 128K x 8 EEPROM Die in One MCM Packaging - Hermetic Ceramic
Configurable to 256K x 16 or 512K x 8
CMOS and TTL Compatible Inputs and Outputs Access Times of 120,140,150, 200, 250& 300ns +5V 10% Supply Automatic Page Write Operation Page Write Cycle Time: 10ms Max Data Retention Ten Years Minimum Low Power CMOS Data Polling for End of Write Detection Industry Standard Pinouts
66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder, Aeroflex code# "P3" 66 Pin, 1.08" x 1.08" x .185" PGA Type, With Shoulder, Aeroflex code# "P7" 68 Lead, .88" x .88" x .200" Dual-Cavity Small Outline Gull Wing, Aeroflex code# "F2" (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint)
MIL-PRF-38534 Compliant MCMs Available Hardware and Software Data Protection Internal Decoupling Capacitors for Low Noise
Operation Commercial, Industrial and Military Temperature Ranges SMD# 5962-94585 Released (P7 & F2)
General Description
Block Diagram - PGA Type Package (P3,P7) & CQFP (F2) The ACT-E128K32 is a high speed, 4 megabit, CMOS EEPROM multichip module (MCM) designed for full temperature range military, space, or high reliability applications. The MCM can be organized as a 256K x 16 bits or 512K x 8 bits device and is input and output CMOS and TTL compatible. Writing is executed when the write enable (WE) and chip enable (CE) inputs are low and output enable (OE) is high. Reading is accomplished when WE is high and CE and OE are both low. Access times grades of 120, 140, 150, 200, 250 & 300ns are standard. The ACT-E128K32 is packaged in a choice of hermetically sealed co-fired ceramic packages, a 66 pin, 1.08" sq PGA or a 68 lead, .88" sq gullwing CQFP. The device operates over the temperature range of -55C to +125C and military environment.
WE1 CE1 WE2 CE2 WE3 CE3 WE4 CE4 A0 - A16 OE 128Kx8 128Kx8 128Kx8
128Kx8
8
8
8
8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
Pin Description I/O0-31 Data I/O
A0-16 Address Inputs WE1-4 Write Enables OE CE1-4 VCC GND Output Enable Chip Enables Power Supply Ground
eroflex Circuit Technology - Advanced Multichip Modules (c) SCD1662 REV B 9/5/01
Absolute Maximum Ratings
Parameter Operating Temperature Storage Temperature Range All Input Voltages with respect to Ground All Output Voltages with respect to Ground Voltage on OE and A9 with respect to Ground Symbol TC TSTG VG Range -55 to +125 -65 to +150 -0.6 to +6.25 -0.6 to VCC+0.6 -0.6 to +13.5 Units C C V V V
NOTICE: Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol VCC VIH VIL TC Parameter Power Supply Voltage Input High Voltage Input Low Voltage Case Operating Temperature (Military) Minimum +4.5 +2.0 -0.5 -55 Maximum +5.5 VCC + 0.3 +0.8 +125 Units V V V C
A
Capacitance
(VIN = 0V, f = 1MHz, TC = 25C)
Symbol CAD COE CWE(1-4) CCE(1-4) CI/O
Parameter A0 - A16 Capacitance Output Enable Capacitance Write Enable Capacitance Chip Enable Capacitance I/O0 - I/O31 Capacitance
Maximum 50 50 20 20 20
Units pF pF pF pF pF
DC Characteristics
(Vcc = 5.0V, Vss = 0V, TC = -55C to +125C, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Supply Current x 32 Mode Operating Supply Current Output Low Voltage Output High Voltage
Sym ILI
Conditions VCC = 5.5V, VIN = GND to VCC
Minimum
Maximum 10 10 250 5 0.45
Units A A mA mA V V
ILOX32 CE = OE = VIH, VOUT = GND to VCC ICCX32 CE = VIL, OE = VIH, f = 5Mhz ISB VOL VOH CE = VIH, OE = VIH, f = 5Mhz IOL = +2.1mA, VCC = 4.5V IOH = -400A, VCC = 4.5V 2.4
Truth Table
CE H L L X X X OE X L H H X L WE X H L X H X Mode Standby Read Write Out Disable Write Inhibit Data I/O High Z Data Out Data In High Z -
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AC Write Characteristics
(VCC = 5V, VSS = 0V, TC = -55C to +125C)
Parameter Write Cycle Time Address Set-up Time Write Pulse Width (WE or CE) Chip Enable Set-up Time Address Hold Time Data Hold Time Chip Enable Hold Time Data Set-up Time Output Enable Set-up Time Output Enable Hold Time
Symbol tWC tAS tWP tCE tAH tDH tCEH tDS tOES tOEH
Min 10 150 0 100 10 0 100 10 10
Max 10
Units ms ns ns ns ns ns ns ns ns ns
A
AC Read Characteristics
(VCC = 5V, VSS = 0V, TC = -55C to +125C)
Read Cycle Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold From Address Change, OE or CE Output Enable to Output Valid Chip Enable or OE to High Z Output
Symbol tRC tACC tACE tOH tOE tDF
-120 Min 120 120 120 0 0 55 70 0 0
-140 140 140 140 0 55 70 0
-150 150 150 150 0 55 70 0
-200 200 200 200 0 55 70 0
-250 250 250 250 0 85 70 0
-300 Max 300 300 300
Max Min
Max Min
Max Min
Max Min
Max Min
Units ns ns ns ns
85 70
ns ns
Page Write Characteristics
(VCC = 5V, VSS = 0V, TC = -55C to +125C)
Parameter Write Cycle Time Address Set-up Time Address Hold Time , See Note 1 Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High Note 1 - Page Address must remain valid for duration of write cycle.
Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH
Minimum 10 100 100 10 150
Maximum 10
Units ms ns ns ns ns ns
150 50
s ns
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Device Operation
The ACT-E128K32 is a high-performance Electrically Erasable and Programmable Read Only Memory. It is composed of four 1 megabit memory chips and is organized as 131,072 by 32 bits. The device offers access times of 120 to 300ns with power dissipation of 1.375W. When the device is deselected, the CMOS standby current is less than 5 mA. The ACT-E128K32 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Aeroflex's ACT-E128K32 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes.
consists of setting the WE line low. The write cycle begins when the last of either CE or WE goes low. The WE line transition from high to low also initiates an internal delay timer to permit page mode operation. Each subsequent WE transition from high to low that occurs before the completion of the tBLC time out will restart the timer from zero. The operation of the timer is the same as a retriggable one-shot.
READ
The ACT-E128K32 stores data at the memory location determined by the address pins. When CE and OE are low and WE is high, this data is present on the outputs. When CE and OE are high, the outputs are in a high impedance state. This two line control prevents bus contention.
A
DATA POLLING
The ACT-E128K32 offers a data polling feature which allows a faster method of writing to the device. Figure 5 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on I/O7 (For each Chip). Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle.
WRITE
A write cycle is initiated when OE is high and a low pulse is on WE or CE with CE or WE low. The address is latched on the falling edge of CE or WE whichever occurs last. The data is latched by the rising edge of CE or WE, whichever occurs first. A byte write operation will automatically continue to completion.
PAGE WRITE OPERATION
The ACT-E128K32 has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within tBLC or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period.
WRITE CYCLE TIMING
Figures 2 and 3 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip enable. Chip enable is accomplished by placing the CE line low. Write enable
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The usual procedure is to increment the least significant address lines from A0 through A6 at each write cycle. In this manner a page of up to 128 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. After the tBLC time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed.
byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. Each 128K byte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer.
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the ACT-E128K32. These are included to improve reliability during normal operation: A) Vcc Sense While below 3.8V typical write cycles are inhibited. B) Write inhibiting Holding OE low and either CE or WE high inhibits write cycles. C) Noise filter Pulses of <10ns (TYP) on WE or CE will not initiate a write cycle.
A
SOFTWARE DATA PROTECTION
A software write protection feature may be enabled or disabled by the user. When shipped by Aeroflex Microelectronics, the ACT-E128K32 has the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. The write protection feature can be disabled by a six
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Data Polling Characteristics
(VCC = 5V, VSS = 0V, TC = -55C to +125C)
Parameter Data Hold Time OE Hold Time OE to Output Valid Write Recovery Time
Guaranteed. But not tested.
Symbol tDH tOEH tOE tWR
Min 10 10
Max
Units ns ns
55 0
ns ns
Figure 1 AC Test Circuit
Current Source IOL
A
Parameter Input Pulse Level Input Rise and Fall
VZ ~ 1.5 V (Bipolar Supply)
Typical 0 - 3.0 5 1.5 50
Units V ns V pF
To Device Under Test CL = 50 pF IOH Current Source
Input and Output Timing Reference Level Output Lead Capacitance
Notes: 1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance.
Figure 2 Write Waveforms - WE Controlled
tWC OE ADDRESS tAS tAH CE tCE WE tWP tDS DATA IN tWPH tDH tCEH tOES tOEH
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Figure 3 Write Waveforms - CE Controlled
tWC OE ADDRESS tAS tAH WE tCE CE tWP tDS DATA IN tWPH tCEH tOES tOEH
A
tDH
Figure 4 Read Waveforms
tRC ADDRESS Address Valid
CE tACE tOE OE tDF tACC tOH
OUTPUT
High Z
Output Valid
Notes: 1. OE may be delayed up to tACS - tOE after the falling edge of CE without impact on tOE or by tACC - tOE after an address change without impact on tACC.
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Figure 5 Data Polling Waveform
WE1-4
CE1-4 tOEH OE tDH I/O7 tOE High Z tWR
A
AN AN AN
ADDRESS
AN
AN
Figure 6 Page Mode Write Waveforms
OE
CEX tWP WEX tAS tAH ADDRESS
Valid ADD
tWPH
tBLC
tDH
tDS DATA
Valid DATA Byte 0 Byte 1 Byte 2 Byte 3
tWC
Byte 127
Notes: 1. A7 through A16 must specify the sector address during each high to low transition of WE (or CE) after the software codes have been entered. 2. OE must be high when WE and CE are both low.
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Figure 7 Software Data Protection Enable Algorithm
(1)
Figure 8 Software Data Protection Disable Algorithm
(1)
Load Data AA To Address 5555
Load Data AA To Address 5555
Load Data 55 To Address 2AAA
Load Data 55 To Address 2AAA
Load Data A0 To Address 5555
Writes Enabled
(2)
Load Data 80 To Address 5555
A
Load Data XX To Any Address (4) Load Data AA To Address 5555 (4)
Load Last Byte To Last Address
Enter Data Protect State
Load Data 55 To Address 2AAA
Load Data 20 To Address 5555
Exit Data Protect State (3)
Load Data XX To Any Address (4)
Load Last Byte To Last Address
NOTES: 1. Data Format: I/O0 - I/O7 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end ot write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded.
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Pin Numbers & Functions 66 Pins -- PGA Type Package
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Function I/O8 I/O9 I/O10 A13 A14 A15 A16 NC I/O0 I/O1 I/O2 WE2 CE2 GND I/O11 A10 A11 Pin # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function A12 Vcc CE1 NC I/O3 I/O15 I/O14 I/O13 I/O12 OE NC WE1 I/O7 I/O6 I/O5 I/O4 I/O24 Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Function I/O25 I/O26 A6 A7 NC A8 A9 I/O16 I/O17 I/O18 VCC CE4 WE4 I/O27 A3 A4 A5 Pin # 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Function WE3 CE3 GND I/O19 I/O31 I/O30 I/O29 I/O28 A0 A1 A2 I/O23 I/O22 I/O21 I/O20
A
Note: Pins 8, 21, 28 & 39 can be connected to ground by specifing Option "C".
"P3" -- 1.08" SQ PGA Type (without shoulder) Package "P7" -- 1.08" SQ PGA Type (with shoulder) Package Bottom View (P7 & P3) Side View (P7)
.185 MAX .025 .035 .050 Pin 56
Side View (P3)
1.085 SQ MAX 1.000 .600 Pin 1
1.030 1.040
.100
1.030 1.040
.100
1.000
.020 .016 .180 TYP
.020 .016 Pin 66 Pin 11 .180 TYP .160 MAX .100
All dimensions in inches
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Pin Numbers & Functions 68 Pins -- Dual-Cavity CQFP
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Function GND CE3 A5 A4 A3 A2 A1 A0 NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Pin # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 Vcc A11 A12 A13 A14 A15 A16 CE1 Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Function OE CE2 NC WE2 WE3 WE4 NC NC NC I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 Pin # 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Function GND I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 VCC A10 A9 A8 A7 A6 WE1 CE4
A
Package Outline -- Dual-Cavity CQFP "F2" Top View
.990 SQ .010 .880 SQ .010
Pin 9 Pin 10
Pin 61 Pin 60 .015 .010
*.200 MAX
.010 REF
.946 .010 0- 7 .050 TYP Pin 26 Pin 27 .800 REF Pin 44 Pin 43
0.010 R
.040 Detail "A" See Detail "A"
.010 .005
*.180 MAX available, call factory for details
All dimensions in inches
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CIRCUIT TECHNOLOGY
Ordering Information
Model Number
ACT-E128K32N-120P7Q ACT-E128K32C-120P7Q ACT-E128K32N-140P7Q ACT-E128K32C-140P7Q ACT-E128K32N-150P7Q ACT-E128K32C-150P7Q ACT-E128K32N-200P7Q ACT-E128K32C-200P7Q ACT-E128K32N-250P7Q ACT-E128K32C-250P7Q ACT-E128K32N-300P7Q ACT-E128K32C-300P7Q ACT-E128K32N-120F2Q ACT-E128K32N-140F2Q ACT-E128K32N-150F2Q ACT-E128K32N-200F2Q ACT-E128K32N-250F2Q ACT-E128K32N-300F2Q
DESC Drawing Number
5962-9458506H4X 5962-9458506H5X 5962-9458505H4X 5962-9458505H5X 5962-9458504H4X 5962-9458504H5X 5962-9458503H4X 5962-9458503H5X 5962-9458502H4X 5962-9458502H5X 5962-9458501H4X 5962-9458501H5X 5962-9458506HMX 5962-9458505HMX 5962-9458504HMX 5962-9458503HMX 5962-9458502HMX 5962-9458501HMX
Speed
120ns 120ns 140ns 140ns 150ns 150ns 200ns 200ns 250ns 250ns 300ns 300ns 120ns 140ns 150ns 200ns 250ns 300ns
Package
PGA Type PGA Type PGA Type PGA Type PGA Type PGA Type PGA Type PGA Type PGA Type PGA Type PGA Type PGA Type CQFP CQFP CQFP CQFP CQFP CQFP
A
Part Number Breakdown
ACT- E 128K 32 N- 200 P7 M
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Memory Type
E = EEPROM
Screening
C = Commercial Temp, 0C to +70C I = Industrial Temp, -40C to +85C T = Military Temp, -55C to +125C M = Military Temp, -55C to +125C, Screening * Q = MIL-PRF-38534 Compliant / SMD
Memory Depth Memory Width, Bits Options
N = None C = Connect to GND - Pins 8,21,28,39 (P3 & P7 Pkg only)
Memory Speed, ns
Package Type & Size Surface Mount Packages Thru-Hole Packages F2 = .88"SQ 68 Lead Dual-Cavity P3 = 1.085"SQ PGA 66 Pins without shoulder CQFP P7 = 1.085"SQ PGA 66 Pins with shoulder
Specifications subject to change without notice.
* Screened to the individual test methods of MIL-STD-883 Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800) 843-1553
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